In the field of digital systems it is often necessary to convert analog signals into digital signals. One kind of analog-to-digital (A/D) signal converter is referred to as a flash ND converter. A flash A/D converter consists of a voltage divider network which divides a reference voltage into a set of successively increasing voltage points. A set of 2.sup.N -1, (N being an integer greater than 0), parallel comparators compare each of the voltage points from the divider to an analog voltage, (Vin). The comparators output either a high or low voltage to indicate whether Vin is less than or greater than each voltage point. For example, all of the comparators coupled to voltage points less than Vin output a voltage corresponding to a first logic level and all of the comparators coupled to voltage points greater than Vin output a voltage corresponding to a second logic level.
The 2.sup.N -1 cumulative first and second logic level signals from the parallel comparators are a digital representation of Vin. Often times this digital representation is fed to a decoder and converted to an N-bit binary digital signal. For an N-bit converter, there are 2.sup.N possible binary codes for describing Vin. The number of bits in the digital word that represents Vin is referred to as the resolution of an A/D converter. For example an A/D converter having a resolution of 4-bits can represent the sampled voltage level in 2.sup.4 or 16 possible binary words. The more bits of resolution the converter can provide, the more accurately it can represent the analog signal.
In addition to the resolution, the flash converter as described above is also characterized by its least significant bit (LSB) voltage. The LSB voltage is equal to the voltage difference between two contiguous voltage points established by the voltage divider network. It directly relates to the resolution of the converter; i.e. small LSBs increase the resolution of the converter. In video A/D converters, the LSB is typically in the millivolt range.
One problem with the flash converter described above is that the comparators are typically non-ideal due to processing fluctuations. As a result, they have built in error voltages, referred to as the off-set voltage (Vos) of the comparator. The ratio of the Vos of a comparator and the converter's LSB defines the differential non-linearity (DNL) of the converter, i.e. DNL=Vos/LSB. If the DNL of a flash A/D converter is greater than .+-.0.50 the converter may lose codes. For example, an N-bit converter generating 2.sup.N possible codes may only be able to generate 2.sup.N -1 codes (or less) if its DNL is too large. As LSB becomes smaller, such as in video applications, this problem can become even more exacerbated. However, small LSBs are desirable since they provide increased resolution
One prior art converter that reduces DNL values while retaining high resolution is a two-stage flash A/D converter. The first stage of this type of converter includes a first voltage divider network and a first stage of parallel comparators that function to perform an initial interpolation step. In addition, the first stage comparators amplify the results of this initial interpolation. In this design, the number of voltage points (provided by the first voltage divider network) and the number of first stage comparators are significantly reduced when compared with the single stage flash converters. As a result, LSB values are larger and DNL values are reduced for this initial first stage comparison. The second stage includes a second voltage divider network and a second set of comparators. The second voltage divider network further divides the voltage outputted by the first stage comparators. Since the first stage comparators amplify their output voltages the LSB of the second voltage divider network is still large enough so that second stage DNL values are in an acceptable range. The second stage voltage divider network is coupled to the second set of comparators. This set of comparators perform a final interpolation of Vin by outputting a voltage corresponding to either a high or low logic level depending on whether the summation of each of the comparators input voltage is positive or negative. The output of the second set of comparators gives the digital representation of Vin.
The first and second voltage dividers in the two-stage converter design described above is typically made-up of either resistive or capacitive elements. If resistors are utilized, the first stage resistors have very low ohmic values (typically around 4 ohms for an 8-bit converter). As a result, they can be fabricated out of metal lines and do not take up much space. However, second stage resistors must have large enough ohmic values (typically 1 Kohm or more for an 8-bit converter) to be driven by the first stage comparators.
In fabricating most digital very large scale integrated (VLSI) circuit designs, a complimentary metal oxide silicon (CMOS) or a bipolar complimentary metal oxide silicon (BiCMOS) process is employed. In general, these processes do not include processing steps for fabricating capacitors or high value resistors such as that required for the two-stage converter. As a result, to fabricate converters requiring high resistive values it is necessary to include additional steps in the standard CMOS or BiCMOS processes. In addition, capacitors or large value resistors take-up large areas in the integrated circuit layout design.
The present invention is a two-stage flash AID converter which obviates the need for large resistive or capacitive elements. In the present invention's converter design, the first stage comparators are directly coupled to the inputs of multiple input second stage comparators. As a result, the size of the present invention's converter is significantly reduced. In addition, the present invention's converter can be fabricated utilizing standard CMOS or BiCMOS processes without the addition of steps to accommodate large resistors or capacitors. Finally, the present invention's converter design reduces the current loading on the output of the first stage of comparators by eliminating the second voltage divider network.